1. Field of the Invention
The present invention relates to the resetting of a group of synchronous and non-transparent memory cells that are series-connected. More particularly, the present invention relates to the resetting of long shift registers, such as those used in cryptographic applications, especially in microcircuit-based cards.
2. Discussion of the Related Art
A non-transparent synchronous cell of a shift register usually has an input stage and an output stage, controlled by means of two clock signals in phase opposition. These clock signals are applied to transfer gates for the transfer of the data elements of each stage. One of the two clock signals activates the holding of a data element in the input stage and its transfer to the output stage. The other clock signal activates the input of a new data element in the input stage and the holding of a previous data element in the output stage.
A shift register is usually reset by the introduction, into each cell, of a circuit capable of imposing a zero at an input when a resetting signal is activated. This circuit generally uses logic gates in synchronization with the control signals for the register. In practice, at least one to two additional transistors must be planned in the input stage and the output stage of each cell to carry out this resetting function. Thus, the resetting circuit soon becomes bulky beyond a certain length of register. For example, in a register with 1024 cells, at least 4096 additional transistors are needed.
Another disadvantage of typical reset circuits is that the synchronizing of the resetting signal with the control signals for the register introduces a delay in the performance of the resetting. Furthermore, this resetting circuit necessitates the conveyance of the signal up to each cell. Beyond a certain length of register, the loss of time that can be attributed to the time of propagation of the active state of the resetting signal to each cell is no longer negligible.
Therefore, it is important, for certain applications of shift registers, to be able to reset their contents almost instantaneously so as not to "expose" the sensitive data contained therein. This is particularly true in the case of cryptographic applications and also for shift registers that work at higher speed.